1. Field of the Invention
The present invention relates to etching of an exposed copper film and an exposed barrier metal film in the production of a semiconductor substrate, and more specifically to a substrate processing method which, by adjusting the etching rate ratio between a copper film, which is to form interconnects on a substrate, and a barrier metal film, can etch the barrier metal film selectively and provide a flattened finish surface.
2. Description of the Related Art
As a technique for forming circuit interconnects on e.g. a silicon substrate, a so-called damascene process, which comprises forming fine interconnect trenches and via holes in a substrate and then embedding copper or a copper alloy in the trenches and via holes to form interconnects, has recently been employed. In the damascene process, chemical mechanical polishing (CMP) is carried out for the formation of interconnects of e.g. copper embedded in the fine trenches and via holes.
Such a damascene process is generally carried out by first forming an inter-level dielectric on a substrate, forming trenches and via holes in the inter-level dielectric, forming a coating film for preventing diffusion of copper, called barrier metal film, on the entire surface, and then depositing an interconnect material, such as copper, on the barrier metal film. Thereafter, CMP is carried out generally in two steps: a first polishing step of primarily polishing the interconnect material, such as copper; and a second polishing step of primarily polishing the barrier metal film. A barrier metal film having a high hardness, such as a Ta film, has recently been employed. For such a barrier metal film, the second step of polishing is effected mainly by mechanical action, rather than chemical action, and a pressure load of several hundred g/cm2 is generally necessary.
The strength of the inter-level dielectric on the substrate varies depending upon the film material. Some inter-level dielectrics cannot endure the pressure load upon the second-step polishing of barrier metal film though they endure the pressure load upon the first-step polishing of copper. In particular, development of inter-level dielectrics having a low dielectric constant, such as a film of a low-k material, is advancing in order to enhance the performance of semiconductor devices through a reduction of the volume of copper damascene interconnects. Such inter-level dielectrics, as compared to common inter-level dielectrics currently used, are especially poor in mechanical strength. Accordingly, even when a cap layer as a protective film is formed on an inter-level dielectric of e.g. a low-k material, peel-off of a layer over the cap layer can occur upon CMP. This makes the application of CMP difficult.
Further, in the generation of ultra low-k materials, only a pressure load of no more than several ten g/cm2 can be applied to an inter-level dielectric. Thus, the use of such an inter-level dielectric makes CMP impracticable for the first-step polishing and the second-step polishing. In view of the above, electrolytic polishing, chemical etching, and the like, may be considered for use in etching of a copper film and a barrier metal film on a substrate.
Electrolytic polishing, however, has the problem that though a copper film can be polished electrolytically, a passive oxide film is formed on the surface of a barrier metal film, e.g. Ta or TaN film, during electrolytic polishing, which retards or stops the progress of electrolytic processing. Chemical etching of a barrier metal film at a practical rate necessitates the use of an acid or oxidizing agent at a high concentration and at a temperature higher than room temperature. Such a chemical etching liquid, however, can cause considerable damage to copper. Even a necessary portion of copper can inevitably be etched if an anticorrosive agent is used.